Flashing

.cargo/config.toml

@@ -3,3 +3,6 @@ target = "thumbv7m-none-eabi"
 rustflags = [
   "-C", "link-arg=-Tlink.x",
 ]
+
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+runner = "arm-none-eabi-gdb -q -x debug/openocd.gdb"

Cargo.toml

@@ -9,4 +9,14 @@ cortex-m-rt = "0.7.5"
 panic-halt = "1.0.0"
 stm32l4xx-hal = { version = "0.7.1", features = ["rt", "stm32l433"] }
 
+[profile.dev]
+opt-level = 1  # we don't fit at 0, and check is nice
+
+[profile.release]
+codegen-units = 1
+debug = true
+lto = true
+opt-level = "z"
+overflow-checks = true
+
 

debug/flash_procs.tcl

@@ -0,0 +1,12 @@
+init
+
+proc flash_stm32 {FILE} {
+    reset halt
+    sleep 100
+    wait_halt 2
+
+    flash write_image erase $FILE
+    verify_image $FILE
+
+    reset run
+}

debug/openocd.cfg

@@ -0,0 +1,6 @@
+source [find interface/cmsis-dap.cfg]
+source [find target/stm32l4x.cfg]
+
+source "flash_procs.tcl"
+
+adapter speed 200

debug/openocd.gdb

@@ -0,0 +1,3 @@
+target extended-remote localhost:3333
+load
+tui layout src

memory.x

@@ -2,8 +2,8 @@ MEMORY
 {
   /* NOTE K = KiBi = 1024 bytes */
   /* TODO Adjust these memory regions to match your device memory layout */
-  FLASH : ORIGIN = 0x8000000, LENGTH = 128K
-  RAM : ORIGIN = 0x20000000, LENGTH = 32K
+  FLASH : ORIGIN = 0x8000000, LENGTH = 256K
+  RAM : ORIGIN = 0x20000000, LENGTH = 64K
 }
 
 /* This is where the call stack will be allocated. */

src/main.rs

@@ -20,7 +20,8 @@ fn main() -> ! {
     // Ok for now, but ideally actually think about what this does (especially when we have tim).
     let clocks = rcc
         .cfgr
-        .hclk(Hertz::MHz(8))
+        .sysclk(Hertz::MHz(64))
+        .pclk1(Hertz::MHz(32))
         .freeze(&mut flash.acr, &mut pwr);
 
     let mut gpioa = dp.GPIOA.split(&mut rcc.ahb2);